A15 LPAE Support

Brief summary of required work, since I was looking at it recently. This is basically a summary of the effects of LPAE noted in the ARM ARM rev C on p1157.

Requirements which QEMU can ignore:
 * optional extra Transient attribute for cacheability
 * Device memory is always Shareable
 * unaligned accesses to Device or SO must fault (no-LPAE is UNPREDICTABLE)

Requirements we need to implement:
 * new long-descriptor translation table format
 * privileged-execute-never attribute in the short-descriptor translation table format
 * DBGDRAR, DBGDSAR are 64 bits
 * DFSR, IFSR, TTBCR have new formats
 * PAR is 64 bits
 * TTBR0, TTBR1 are 64 bits
 * new regs MAIRn replace PRRR and NMRR
 * two new regs AMAIRn
 * ldrd/strd to 64-bit-aligned addresses are 64-bit single-copy atomic (probably ignorable for now)

I'm going to include "switch QEMU's target_phys_addr_t type from 32 to 64 bits" in this work.

Work items:
Privileged-execute-never attribute in short-descriptor format: DONE
Fault status register format changes -- DFSR, IFSR: DONE
Register changes -- TTBCR, TTBR0, TTBR1: DONE
Make v-to-p cp15 ops work 64 bit, ie 64 bit PAR: DONE
Implement dummy no-op AMAIR0/AMAIR1: DONE
Handle PRRR/NMRR becoming MAIR0/MAIR1 for long format: DONE
Implement long-descriptor translation table format: DONE
Make sure v-to-p code is using target_phys_addr_t not uint32_t: DONE
Make debug registers DBGDRAR, DBGDSAR 64 bit: DONE
Get patches fixing compile failures with 64 bit physaddrs upstream: DONE
Test and benchmark 64 bit physaddr to confirm no breakage: DONE
Submit patches switching to 64 bit physaddr: DONE
Allow vexpress-a15 model and arm boot code to take more than 4GB of RAM: DONE
Get LPAE patches through code review and into master: DONE
Get vexpress/arm_boot patches into master: DONE